The present invention relates to a semiconductor device having a capacitor using a metal oxide film as a dielectric film, and a manufacturing method therefor.
As the integration degree of an integrated circuit is increasing, demands have arisen for an increase in memory capacity by decreasing the memory cell area in a DRAM (Dynamic Random Access Memory) made up of one transistor and one capacitor. To meet these demands, there is proposed a technique of increasing the capacity without increasing the memory cell area by using a material such as tantalum oxide (Ta2O5) having a high permittivity for a dielectric film which forms the capacitor.
When a material having a higher permittivity, e.g., tantalum oxide is used as a dielectric film, a desired permittivity is obtained by forming a tantalum oxide film and performing post-processing such as annealing and plasma processing. At this time, post-processing is generally done in an oxygen-containing atmosphere in order to prevent elimination of oxygen from the dielectric material as an oxide. For this reason, tungsten or titanium nitride used for a storage electrode oxidizes. A metal material such as gold, platinum, or ruthenium which hardly oxidizes or exhibits conductivity even upon oxidization is used.
A DRAM using such a dielectric film will be explained by exemplifying a stacked memory cell.
As shown in FIG. 10, a gate electrode 1004 is formed via a gate insulating film 1003 in a region defined by an element isolation region 1002 on a semiconductor substrate 1001. Source and drain regions 1005a and 1005b are formed on the two sides of the gate electrode 1004 on the semiconductor substrate 1001 by forming impurity regions by ion implantation using the gate electrode 1004 as a mask. The gate electrode 1004, gate insulating film 1003, and source and drain regions 1005a and 1005b constitute one transistor TR.
An interlevel insulating film 1006 is formed on the gate electrode 1004 in the entire region of the semiconductor substrate 1001. A contact plug 1007 connected to the drain region 1005b formed in the semiconductor substrate 1001 is formed at a predetermined position in the interlevel insulating film 1006. A bit line 1008 connected to the contact plug 1007 is formed.
An interlevel insulating film 1009 is formed on the interlevel insulating film 1006 including the bit line 1008. A contact plug 1010 connected to the source region 1005a formed in the semiconductor substrate 1001 extends through the interlevel insulating films 1009 and 1006.
A stacked ruthenium storage electrode 1011 is formed on the contact plug 1010.
A capacitor insulating film 1012 is formed on the storage electrode 1011 to cover it, and a plate electrode 1013 is formed on the capacitor insulating film 1012.
In this structure, one memory cell is constituted by the transistor TR having the gate electrode 1004, and a capacitor made up of the storage electrode 1011, capacitor insulating film 1012, and plate electrode 1013 connected to the transistor.
An interlevel insulating film 1014 of an insulator is formed on the interlevel insulating film 1009 including the plate electrode 1013. Although not shown, an interconnection layer connected to the bit line 1008 and plate electrode 1013 is formed on the interlevel insulating film 1014.
In this semiconductor device, a contact plug connected to a silicon substrate generally uses heat-resistant doped polysilicon or a refractory metal such as tungsten.
In the conventional structure, high-temperature processing is performed in an oxygen atmosphere after forming the capacitor insulating film in order to attain a desired permittivity.
In high-temperature processing in an oxygen atmosphere, oxygen readily permeates through the ruthenium storage electrode. This oxidizes the surface of the contact plug, forms a capacitance at the interface between the storage electrode and the contact plug, and increases the resistance.